The present invention relates in general to electronic circuits and systems and in particular to a memory architecture and systems and methods using the same.
Dynamic random access memories (DRAMs) typically include an array of rows and columns of memory cells, each row associated with a conductive wordline and each physical column with a conductive bitline. The array is normally partitioned into a number of subarrays to efficiently access the cells. For addressing purposes, a xe2x80x9ccolumnxe2x80x9d is one or more physical columns of cells which are addressed and accessed at once (e.g. in a xe2x80x9cby 16xe2x80x3xe2x80x9d device, a column is 16 physical columns wide). By appropriate addressing of the rows and columns, data can be read and written into a predetermined cell or set of cells.
Consider the case of a read to a subarray (a write is basically the same with the data flow reversed). Row addressing circuitry, in response to a row address, activates the conductive wordline containing the data to be accessed. In turn, the pass transistors (transfer gates) of all memory cells along the row are activated thereby coupling the capacitor of each of these cells to their associated bitline, all of the bitlines in the subarray having been previously precharged to a predetermined voltage. As a result, a small positive or negative voltage shift from the precharge voltage occurs on each bitline, depending on the voltage stored on the capacitor of the associated cell. Sense amplifiers sense the voltage change on each bitline and latch each bitline to a corresponding logic high or logic low voltage. Words of one or more cells, depending on the column width, can then be output by a column decoder coupled to the sense amplifiers and associated bitlines. There are various ways in which data can be output from the column decoder during a read, including: random, page, serial and burst accesses. Briefly, during a random access a single word of data from a single addressable column along the active row is passed to the DRAM output by the column decoder. Once the word is output, a new access to the array is initiated with a new row address. During a page access, a row is selected with a row address and a first word is accessed using a first column address, typically input from an external source. Then, while the same row remains active, additional column addresses, generated either internal or external to the DRAM, are used to access additional words from that row. In a page access, these data do not have to be accessed from adjacent columns along the active row. During a serial access, data from the sense amplifiers are serialized and then clocked out of the DRAM using a single output pin.
In a burst access, a row is again selected as described above and the stored data along that row correspondingly latched into the sense amplifiers. One or more bits are set in a mode register defining a burst length in number of words. From a given starting column address, adjacent columns are sequentially accessed by the column decoder in response to a clock until the entire burst of words defined by the burst length is accessed.
Burst accessing is an important feature in many types of DRAMs, and in particular synchronous DRAMs (SDRAMs). Unfortunately, currently significant problems are encountered during the design and implementation of DRAMs with burst mode capability. Among other things, it currently is not possible to access data from the same subarray at high or very high data rates. This can significantly put restrictions on minimizing burst access time and consequently limits the usefulness of current DRAMs in high speed applications.
Thus, the need has arisen for an improved architecture for implementing DRAMs with high speed access capability. In particular, the present restrictions on very high speed bursting from a subarray should be addressed.
According to a first embodiment of the principles of the present invention, a memory architecture is disclosed which includes an array of memory cells partitioned into a plurality of subarrays. Each subarray includes a plurality of memory cells organized in rows and columns, each row associated with a conductive wordline and each column associated with a pair of conductive half-bitlines. First and second sense amplifiers are selectively coupled to a selected pair of half-bitlines. A first I/O line is coupled to the first sense amplifier and a second I/O line is coupled to the second sense amplifier. First and second sets of global I/O lines, are each selectively coupled to the first and second local I/O lines.
According to a second embodiment of the principles of the present invention, memory is provided including an array of rows and columns of memory cells, each row controlled by a first conductor and each column controlled by a second conductor. A plurality of sense amplifiers is coupled to a corresponding one of the second conductors. Also included are at least one input/output line and at least one transfer gate for selectively coupling an output of a selected one of the sense amplifiers to the input/output line, the transfer gate operable in response to a control signal associated with the selected sense amplifier. Latches coupled to the input/output line for latching data output from the selected sense amplifier is presented on the input/output line in a response to a control signal.
According to a third embodiment of the principles of the present invention, a memory is disclosed which includes a first memory cell coupled to a wordline and a first bitline and a second memory cell coupled to the wordline and a second bitline. First and second sense amplifiers are each coupled to the first and second bitlines. A third sense amplifier is selectively coupled to the second sense amplifier by a third bitline for copying data received from the second sense amplifier. A first read amplifier is selectively coupled to the third sense amplifier for outputing data transferred from the first memory cell by the second and third sense amplifiers. A second read amplifier is selectively coupled to the third sense amplifier outputting data transferred from the second memory cell by the first, second, and third sense amplifiers.
The principles of the present invention are also embodied in methods for storing and retrieving data. In one such embodiment, a method of bursting data from first and second memory cells is disclosed, the first memory cell coupled to a wordline and a first bitline and the second memory cell coupled to the wordline and a second bitline. The wordline is asserted, and first data stored in the first cell is latched with a first sense amplifier selectively coupled to the first bitline. Second data, stored in the second cell, is latched with a second sense amplifier selectively coupled to the second bitline. The first data latched in the first sense amplifier is copied into a third sense amplifier coupled to the first sense amplifier by a third bitline. The data copied into third sense amplifier is transferred to peripheral circuitry. The second data latched in the second sense amplifier is copied into a fourth sense amplifier through a fourth bitline. The second data copied into the fourth sense amplifier is transferred to the peripheral circuitry.
According to another method embodying the principles of the present invention, a method of bursting data in a multiple subarray memory is disclosed, where each subarray is arranged in rows and columns with each column of cells coupled to a conductive bitline and each bitline selectively coupled to first and second sense amplifiers. First and second sets of input/output lines are precharged. Data from first and second memory cells with the subarray are latched through the corresponding first and second bitlines of the subarray into first and second sense amplifiers. The data latched in the second sense amplifier is copied into a third sense amplifier. Data from the first cell is accessed using the first sense amplifier and the first set of input/output lines. Data from the second cell is accessed using the third sense amplifier and the second set of input/output lines.
In an additional embodiment of the present invention, memory is disclosed including an array of rows and columns of subarrays, each subarray including a plurality of rows and columns of memory cells, with each column of cells associated with a bitline and each bitline coupled to first and second sense amplifiers. Circuitry is provided for coupling the bitlines of a selected subarray, a column of subarrays to peripheral circuitry through the bitlines of a second subarray of the column. Circuitry is also provided for selectively activating a set of the sense amplifiers coupled to the bitlines of the first and second subarrays.
In two further embodiments of the principles of the present invention, a memory is disclosed which includes an array of rows and columns of sense amplifiers. Circuitry is provided for selectively coupling an I/O port of a selected sense amplifier of a selected column with an I/O line in response to a control signal. Circuitry is also provided for selectively coupling a control signal from a column line to the circuitry for selectively coupling an I/O port to the I/O line.
The principles of the present invention have substantial advantages over the prior art. Among other things, two accesses can sequentially be made to the same subarray per array during a single RAS cycle. This capability is not available in the current art. Applying the principles of the present invention allows for the design and fabrication of DRAMs with high-speed access capability and in particular, DRAMs with very high speed bursting capability.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and the specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.